Technical Field
The present disclosure relates to a control module for a switching converter, which includes an estimator of an input electric quantity. In addition, the present disclosure relates to a method for controlling a switching converter.
Description of the Related Art
As is known, there exist various types of switching converters, amongst which there may, for example, be cited flyback, boost, and buck converters.
In general, in the field of switching converters there is particularly felt the need to have available converters that are characterized by a high power factor, as well as a low total harmonic distortion (THD) and a low zero-load power dissipation. In order to obtain the aforementioned characteristics, switching converters are known that implement, for example, a circuit layout of the type illustrated in FIG. 1.
In detail, FIG. 1 shows a switching power supply 1 of a flyback type, referred to hereinafter as “flyback power supply 1”.
In greater detail, the flyback power supply 1 includes a bridge rectifier 2, which has two input terminals, designed to receive an a.c. voltage from a supply line, and a first output terminal and a second output terminal, which are connected, respectively, to a first ground and to a first terminal of a filtering capacitor Cin, the second terminal of which is connected to the first ground. The bridge rectifier 2 supplies on its own second output terminal a voltage Vin(θ), referred to hereinafter as “input voltage Vin(θ)”, where θ is the phase of the a.c. voltage present on the supply line.
The flyback power supply 1 further comprises a flyback converter 3, which on the primary side includes, in addition to the filtering capacitor Cin, a transformer 4, which comprises a first inductor Lp and a second inductor Ls, which function respectively as primary winding Lp and secondary winding Ls and share a same magnetic core, referred to hereinafter as “core of the transformer 4”. Furthermore, the transformer 4 comprises an auxiliary winding Laux. A first terminal of the primary winding Lp is connected to the first terminal of the filtering capacitor Cin.
The flyback converter 3 further comprises a control module 15, a resistive divider 16, which includes a first resistor Ra and a second resistor Rb, and a transistor M formed, for example, by a power MOSFET.
The first resistor Ra has a first terminal and a second terminal, which are connected, respectively, to the first terminal of the filtering capacitor Cin and to a first terminal of the second resistor Rb, the second terminal of which is connected to the first ground. In practice, the second terminal of the first resistor Ra and the first terminal of the second resistor Rb form a node electrically coinciding with a first input terminal MULT of the control module 15.
The flyback converter 3 further comprises a third resistor RZCD and a fourth resistor Rs. The first and second terminals of the third resistor RZCD are connected, respectively, to the first terminal of the auxiliary winding Laux, the second terminal of which is connected to the first ground, and to a second input terminal ZCD of the control module 15. The first and second terminals of the fourth resistor Rs are connected, respectively, to the source terminal of the transistor M and to the first ground. Further, the first terminal of the fourth resistor Rs is connected to a third input terminal CS of the control module 15. Once again with reference to the transistor M, the drain terminal is connected to the second terminal of the primary winding Lp, whereas the gate terminal is connected to an output terminal GD of the control module 15, which further includes a feedback terminal FB, described hereinafter, and a fourth input terminal GND, connected to the first ground.
In practice, the fourth resistor Rs enables detection of the current that flows in the primary winding Lp when the transistor M is on. In FIG. 1, the current that flows in the fourth resistor Rs is designated by Ip (t,θ).
The flyback converter 3 further comprises a clamping circuit 20, which is arranged between the first and second terminals of the primary winding Lp for limiting the spikes of the voltage present on the drain terminal of the transistor M, caused, for example, by parasitic inductances.
On its own secondary side, the flyback converter 3 comprises a feedback circuit 22, a diode D, referred to hereinafter as “output diode D”, and a further capacitor Cout, referred to hereinafter as “output capacitor Cout”; typically, the output capacitor Cout is of an electrolytic type.
The anode of the output diode D is connected to a first terminal of the secondary winding Ls, whereas the cathode is connected to a first terminal of the output capacitor Cout, the second terminal of which is connected to a second ground, as on the other hand also the second terminal of the secondary winding Ls. In general, the voltage across the output capacitor Cout is referred to hereinafter as “output voltage Vout”. Further, the output voltage Vout represents the voltage that is to be regulated by the flyback converter 3. In FIG. 1, the current that flows in the output diode D is designated by Is(t,θ).
The feedback circuit 22 is connected to the first terminal of the output capacitor Cout and to the feedback terminal FB of the control module 15. In addition, the feedback circuit 22 is configured to generate an error signal proportional to the difference between the output voltage Vout and a reference voltage, as well as for transferring the error signal on the primary side of the flyback converter 3, generally using an opto-coupler. This transfer entails generation of a control voltage Vc on the primary side, and in particular on the feedback terminal FB of the control module 15. In this connection, the control module 15 generates on a own node an internal voltage Vint, and further has a fifth resistor Rc, which is arranged between the aforementioned node and the feedback terminal FB of the control module 15. Furthermore, the control module 15 and the feedback circuit 22 are coupled in such a way that, at output from the feedback terminal FB of the control module 15, a current IFB is present that depends upon the aforementioned error signal. The current IFB causes a voltage drop on the fifth resistor Rc. The aforementioned control voltage Vc is, precisely, the voltage present on the feedback terminal FB of the control module 15 and depends upon the error signal in such a way as to regulate the output voltage Vout. To a first approximation, the control voltage Vc may be considered constant because the band of the control loop is much lower than the frequency of the input voltage Vin(θ).
The control module 15 further comprises a multiplier 24, a comparator 26, a flip-flop 28 of a set-reset type, a driver 30, a starter circuit 32, a first logic gate 34 of an OR type, and a circuit 36 referred to hereinafter as “zero-current detection circuit 36”.
In detail, the multiplier 24 has a first input, connected to the feedback terminal FB of the control module 15 for receiving the control voltage Vc, and a second input, connected to the first input terminal MULT for receiving the voltage present thereon, which is proportional to the input voltage Vin(θ) through the division ratio R2/(R1+R2) introduced by the resistive divider 16, where R1 and R2 are the values of resistance of the first and second resistors Ra, Rb. The multiplier 24 generates a voltage VcsREF(θ) on an own output, which is connected to a negative input terminal of the comparator 26. The voltage VcsREF (θ) has the form of a rectified sinusoid, the amplitude of which depends upon the control voltage Vc and the effective voltage present on the supply line.
The positive input terminal of the comparator 26 is connected to the third input terminal CS of the control module 15 for receiving the voltage (designated by Vcs(t,θ)) present on the fourth resistor Rs. The voltage Vcs(t,θ) is directly proportional to the current present in the primary winding Lp when the transistor M is in conduction, i.e., during magnetization of the primary winding Lp itself.
The output of the comparator 26 is connected to the reset input of the flip-flop 28, the output of which (designated by Q) is connected to the input of the driver 30, the output of which forms the output terminal GD of the control module 15. The output of the flip-flop 28 is further connected to the set input of the flip-flop 28 itself, by interposition of the starter circuit 32. In particular, the input of the starter circuit 32 is connected to the output Q of the flip-flop 28, whereas the output of the starter circuit 32 is connected to a first input of the first logic gate 34. The second input and the output of the first logic gate 34 are connected, respectively, to the output of the zero-current detection circuit 36 and to the set input of the flip-flop 28. The input of the ZCD circuit 36 is connected to the second input terminal ZCD of the control module 15.
In use, assuming that the transistor M is on, there occurs a linear growth of the current Ip(t,θ) in the primary winding Lp and hence of the voltage Vcs(t,θ). When the voltage Vcs(t,θ) becomes equal to the voltage VcsREF(θ), the comparator 26 resets the output of the flip-flop 28, and the transistor M is turned off. Consequently, the voltage supplied by the resistive divider 16, which has the form of a rectified sinusoid, determines the peak value of the current in the primary winding Lp, which is thus enveloped by a rectified sinusoid.
When the transistor M turns off, the energy stored in the primary winding Lp is transferred by magnetic coupling to the secondary winding Ls, and hence in the output capacitor Cout until the secondary winding Ls demagnetizes. Furthermore, as long as a current flows in the secondary winding Ls, the voltage of the drain terminal of the transistor M is equal to Vin(θ)+VR, where VR is the so-called reflected voltage, equal to n·Vout, where n is the ratio between the number of the turns of the primary winding Lp and the number of the turns of the secondary winding Ls of the transformer 4.
Following upon demagnetization of the secondary winding Ls, the output diode D opens, and the drain terminal of the transistor M becomes floating and tends to assume a voltage equal to the input voltage Vin(θ) through damped oscillations caused by a parasitic capacitance resonating with the primary winding Lp. However, the fast drop in voltage that takes place on the drain terminal of the transistor M following upon demagnetization of the transformer 4 is coupled to the second input terminal ZCD of the control module 15 through the auxiliary winding Laux and the third resistor RZCD. Furthermore, the zero-current detection circuit 36 generates a pulse whenever it detects that a falling edge of the voltage present on its own input drops below a threshold. This pulse forces a corresponding change of the output of the flip-flop 28 and consequently leads to turning-on of the transistor M and start of a new switching cycle.
The starter circuit 32 enables start of the first switching cycle after turning-on of the flyback converter 3, i.e., when no signal is yet present on the second input terminal ZCD of the control module 15, and further prevents the flyback converter 3 from remaining blocked if for any reason the signal on the second input terminal ZCD of the control module 15 is lost.
Examples of the signals that are generated in use within the flyback converter 3 are illustrated in FIG. 2, which, in addition to the aforementioned quantities Ip (t,θ), Is (t,θ), Vcs(t,θ), VcsREF (θ), shows:                the voltage VDS between the drain and source terminals of the transistor M;        the voltage Vin,pk sin θ, where Vin,pk is the peak value of the input voltage Vin;        the voltage Vaux present on the auxiliary winding Laux;        the voltage VZCD present on the second input terminal ZCD of the control module 15;        the thresholds VZCDarm and VZCDtrig of the voltage VZCD at which the zero-current detection circuit 36 is armed and generates a pulse, respectively;        the state ARM of the zero-current detection circuit 36;        the signal sS (of a logic type) present on the set input of the flip-flop 28, and hence the pulses TRIGGER generated by the zero-current detection circuit 36;        the signal sR (of a logic type) present on the reset input of the flip-flop 28;        the signal sGD (of a logic type) present on the output Q of the flip-flop 28, which governs turning-on of the transistor M (it is assumed that the driver 30 does not introduce any delay); and        a so-called “freewheel” state FW, corresponding to the period in which there occurs demagnetization of the transformer 4.        
In general, it should be noted that, in indicating the quantities, the fact of not rendering any dependence upon parameters (in the case in point, the phase θ or the time t) explicit does not imply that the quantity in question is necessarily constant.
In addition, FIG. 2 represents the following periods:                the period TON, in which the transistor M is on, i.e., in conduction, and hence the period in which the core of the transformer 4 is magnetized;        the period TFW, in which demagnetization of the core of the transformer 4 occurs; and        the period TR, i.e., the delay that elapses between complete demagnetization of the core of the transformer 4 and next turning-on of the transistor M, i.e., start of new magnetization of the core of the transformer 4.        
The resulting plots of the currents Ip(t,θ), Is(t,θ), as well as the corresponding envelopes of the corresponding peaks Ipkp(θ), Ipks(θ) and the average, cycle by cycle, Iin(θ) of the current in the primary winding Lp are illustrated in FIG. 3. For completeness, designating by T the switching period, we have T=TFW+TR+TON.
For practical purposes, the flyback converter 3 is of the quasi-resonant type. In fact, turning-on of the transistor M is synchronized with the instant of complete demagnetization of the transformer 4 (i.e., with the instant when the current in the secondary winding Ls becomes zero), albeit with a delay such that it occurs at a so-called “valley” of the voltage VDS. Turning-off of the transistor M is, instead, determined by detecting the moment when the current in the primary winding Lp reaches a given value. Furthermore, the flyback converter 3 is of the current-mode control type, and in particular of the peak-current-mode control type. In addition, since the peak envelope of the current that flows in the fourth resistor Rs, and hence in the primary winding Lp, is sinusoidal, a power factor higher than 0.9 is obtained.
In practice, as illustrated in FIG. 4, the flyback converter 3 implements an electrical layout formed by a conversion stage 40, which is operatively coupled to the control module 15. In particular, the conversion stage 40 receives at input the input voltage Vin(θ) and is controlled by the control module 15 in such a way as to supply the output voltage Vout. As illustrated in FIG. 4, control of the conversion stage 40 occurs thanks to the aforementioned signal sGD (more precisely, thanks to the voltage VGA present on the gate terminal of the transistor M), as well as thanks to the voltage VZCD. Further, even though not illustrated in FIG. 2, the conversion stage 40 is controlled also on the basis of the feedback present between the output of the conversion stage 40 and the control module 15. In addition, in order to control the conversion stage 40, the control module 15 receives at input, through the resistive divider 16, a fraction of the input voltage Vin(θ), designated by VMULT in FIG. 4.
FIG. 5 shows a further example of converter, and in particular shows a boost converter 50, which is here described just as regards the differences with respect to the flyback converter 3. In FIG. 5, components already illustrated in FIG. 1 have the same reference numbers, except where otherwise specified. The clamping circuit 20 is absent.
In detail, instead of the transformer 4, a coupled inductor 54 is present, which includes the primary winding and the auxiliary winding, designated, respectively, by L1 and Laux, but not the secondary winding. The primary winding and the auxiliary winding L1 and Laux share a same magnetic core. The first terminal of the primary winding L1 is still connected to the first terminal of the filtering capacitor Cin, but the second terminal is connected to the anode of the output diode D. The auxiliary winding Laux is electrically connected as in the case of the flyback converter 3 and performs the same electrical function. The drain terminal of the transistor M is still connected to the second terminal of the primary winding L1. Hence, it is now connected to the anode of the output diode D.
The feedback circuit, designated by 52, comprises a sixth resistor Rd and a seventh resistor Re, which form a corresponding resistive divider, which is arranged between the cathode of the output diode D and ground and the central node of which is connected to the feedback terminal FB of the control module, here designated by 55.
The control module 55 comprises, instead of the fifth resistor Rc, an amplifier 58, referred to hereinafter as “error amplifier 58”. The non-inverting terminal of the error amplifier 58 is connected to a reference node, which is set at an internal reference voltage Vref_int, whereas the non-inverting terminal forms the feedback terminal FB of the control module 55. The output of the error amplifier 58 is connected to the first input of the multiplier 24, the second input of which is still connected to the resistive divider 16. The output of the multiplier 24 is connected to the negative input terminal of the comparator 26, the positive input terminal of which is connected to the third input terminal CS of the control module 55.
The boost converter 50 further comprises a loop-compensation circuit 60, which extends between a respective first node and a respective second node and includes an eighth resistor Rf and a ninth resistor Rg, as well as a further capacitor 62, referred to hereinafter as “additional capacitor 62”. In particular, the eighth resistor Rf is arranged between the aforementioned first and second nodes of the loop-compensation circuit 60 and is arranged in parallel to the series circuit formed by the additional capacitor 62 and by the ninth resistor Rg. Furthermore, the first node of the loop-compensation circuit 60 is connected to the feedback terminal FB of the control module 55, whereas the second node of the loop-compensation circuit 60 is connected to the output of the error amplifier 58.
In practice, the error amplifier 58 compares a portion of the output voltage Vout with the internal reference voltage Vref_int and generates the control voltage Vc, which depends upon an error signal proportional to the deviation between the aforementioned portion of the output voltage Vout and the internal reference voltage Vref_int for regulating the output voltage Vout. As explained previously, to a first approximation, the control voltage Vc may be considered constant. The subsequent operation of the boost converter 50 is similar to that of the flyback converter 3. Examples of the time plots of the signals sS, sR, sGD and of the current I(t,θ) in the primary winding L1 are illustrated in FIGS. 6a and 6b. Further, FIG. 6a shows a signal sZCD indicating the period in which the current iL through the primary winding L1 is zero.
In greater detail, the boost converter 50 operates in the so-called “transition mode” (TM) since the current in the primary winding L1 vanishes for a short period of time.
This being said, irrespective of the topology of the switching converter considered (flyback, boost, buck, etc.), there occurs generation of a sinusoidal reference, by a sort of line-sensing circuitry that includes a resistive divider and enables detection of a percentage of the rectified line voltage. This entails a dissipation on the resistive divider, which, according to the application and the corresponding sizing of the switching converter, may range between about ten milliwatts and some tens of milliwatts. This loss is hence not negligible and the desire to reduce it as much as possible is particularly felt.